View MAX1291ACEI-T_6082409.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

___________________________________ max19515???/?(adc)10?? ?65msps? max19515??0.4v1.4v??? ?rfif???? ??400mhz????max19515 ?????? (zif)???(if) ???f in = 70mhzf clk = 65mhz? (snr)?60.1dbfs??(sfdr)?82dbc max195151.8v????? ?2.5v3.3v?(avdd) 1.8v3.5v?(ovdd)v avdd = 1.8v?? ????43mw????? max19515????1??1mw??1 ??15mw ?3??????????? ????????? ???????? ???cmos?? ?cmos? max19515?7mm x 7mm48?qfn ?-40 c+85 c??? ???865msps100msps?130msps? ?max19505max19506?max19507 ????10100msps130msps? max19516max19517? ___________________________________ ? if???????? ?? ?????? ? ___________________________________ ? ????(65msps?43mw/?) ? 1.8v2.5v3.3v??? ? ?? 70mhz?snr?60.1dbfs 70mhz?sfdr?82dbc ? ?spi tm ???????? ? ?(?cmoscmos) ? dclk???? ? ? ????(0.4v1.4v) ? ?(> 850mhz) ? ?? ? ?? ? 1?(div1)2?(div2)?4?(div4)??? ? ??????? ? ??(dor) ? cmos???(?) ? ??() ? ? ? ?7mm x 7mm48?qfn? ? max19515 ??1065msps adc ________________________________________________________________ maxim integrated products 1 _______________________________ ? 19-4195; rev 3; 1/11 /v? + ??(pb)/rohs??? * ep = ?? ? spimotorola, inc.?? ? ??????????????? ?????maxim?10800 852 1249 ()10800 152 1249 () maxim?china.maxim-ic.com part temp range pin-package max19515etm+ -40? to +85? 48 tqfn-ep* max19515etm/v+ -40? to +85? 48 tqfn-ep*
max19515 ??1065msps adc 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 65mhz, a in = -0.5dbfs, data output termination = 50?, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ovdd, avdd to gnd............................................-0.3v to +3.6v cma, cmb, refio, ina+, ina-, inb+, inb- to gnd ......................................................-0.3v to +2.1v clk+, clk-, sync, spen, cs, sclk, sdin to gnd ..........-0.3v to the lower of (v avdd + 0.3v) and +3.6v dclka, dclkb, d9a?0a, d9b?0b, dora, dorb to gnd..........-0.3v to the lower of (v ovdd + 0.3v) and +3.6v continuous power dissipation (t a = +70?) 48-pin thin qfn, 7mm x 7mm x 0.8mm (derate 40mw/? above +70?).............................................................3200mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units dc accuracy resolution 10 bits integral nonlinearity inl f in = 3mhz -0.8 ?.25 +0.8 lsb differential nonlinearity dnl f in = 3mhz -0.7 ?.2 +0.7 lsb offset error oe internal reference -0.4 ?.1 +0.4 %fs gain error ge external reference = 1.25v -1.5 ?.3 +1.5 %fs analog inputs (ina+, ina-, inb+, inb-) (figure 3) differential input-voltage range v diff differential or single-ended inputs 1.5 v p-p common-mode input-voltage range v cm (note 2) 0.4 1.4 v fixed resistance > 100 input resistance r in differential input resistance, common mode connected to inputs 4 k? input current i in switched capacitance input current, each input 35 ? c par fixed capacitance to ground, each input 0.7 input capacitance c sample switched capacitance, each input 1.2 pf conversion rate maximum clock frequency f clk 65 mhz minimum clock frequency f clk 30 mhz data latency figures 9, 10 9 cycles
max19515 ??1065msps adc _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units dynamic performance small-signal noise floor ssnf f in = 70mhz, < -35dbfs -60.4 dbfs f in = 3mhz 60.2 f in = 70mhz 59.3 60.1 signal-to-noise ratio snr f in = 175mhz 59.8 dbfs f in = 3mhz 59.7 f in = 70mhz 58.8 59.6 signal-to-noise plus distortion ratio sinad f in = 175mhz 59.3 db f in = 3mhz 85 f in = 70mhz 73 84 spurious-free dynamic range (2nd and 3rd harmonic) sfdr1 f in = 175mhz 81 dbc f in = 3mhz 82 f in = 70mhz 74.4 82 spurious-free dynamic range (4th and higher harmonics) sfdr2 f in = 175mhz 82 dbc f in = 3mhz -86 f in = 70mhz -86 -73 second harmonic hd2 f in = 175mhz -82 dbc f in = 3mhz -86 f in = 70mhz -86 -74 third harmonic hd3 f in = 175mhz -82 dbc f in = 3mhz -80 f in = 70mhz -79 -71.8 total harmonic distortion thd f in = 175mhz -77 dbc f in = 70mhz ?.5mhz, -7dbfs -90 third-order intermodulation im3 f in = 175mhz ?.5mhz, -7dbfs -80 dbc full-power bandwidth fpbw 850 mhz aperture delay t ad 850 ps aperture jitter t aj 0.3 ps rms overdrive recovery time ?0% beyond full scale 1 cycles electrical characteristics (continued) (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 65mhz, a in = -0.5dbfs, data output termination = 50?, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1)
max19515 ??1065msps adc 4 _______________________________________________________________________________________ electrical characteristics (continued) (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 65mhz, a in = -0.5dbfs, data output termination = 50?, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units interchannel characteristics f ina or f inb = 70mhz at -1dbfs 95 crosstalk f ina or f inb = 175mhz at -1dbfs 85 dbc gain match f in = 70mhz ?.05 db offset match f in = 70mhz ?.1 %fsr phase match f in = 70mhz ?.5 d eg r ees analog outputs (cma, cmb) cma, cmb output voltage v com default programmable setting 0.85 0.9 0.95 v internal reference refio output voltage v refout 1.23 1.25 1.27 v refio temperature coefficient tc ref < ?0 ppm/? external reference refio input-voltage range v refin 1.25 +5/ -10% v refio input resistance r refin 10 ?0% k? clock inputs (clk+, clk-)?ifferential mode differential clock input voltage 0.4 to 2.0 v p-p self-biased 1.2 differential input common-mode voltage dc-coupled clock signal 1.0 to 1.4 v differential, default 10 k ? differential, internal termination selected 100 ? input resistance r clk common mode 9 k? input capacitance c clk to ground, each input 3 pf clock inputs (clk+, clk-)?ingle-ended mode (v clk- < 0.1v) single-ended mode selection threshold (v clk- ) 0.1 v allowable logic swing (v clk+ ) 0 - v avdd v single-ended clock input high threshold (v clk+ ) 1.5 v single-ended clock input low threshold (v clk+ ) 0.3 v v clk+ = v avdd = 1.8v or 3.3v +0.5 input leakage (clk+) v clk+ = 0v -0.5 ? input leakage (clk-) v clk- = 0v -150 -50 ? input capacitance (clk+) 3 pf
max19515 ??1065msps adc _______________________________________________________________________________________ 5 electrical characteristics (continued) (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 65mhz, a in = -0.5dbfs, data output termination = 50?, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units clock input (sync) allowable logic swing 0 - v avdd v sync clock input high threshold 1.5 v sync clock input low threshold 0.3 v v sync = v avdd = 1.8v or 3.3v +0.5 input leakage v sync = 0v -0.5 ? input capacitance 4.5 pf digital inputs (shdn, cs) allowable logic swing 0 - v avdd v input high threshold 1.5 v input low threshold 0.3 v v shdn /v spen = v avdd = 1.8v or 3.3v +0.5 input leakage v shdn /v spen = 0v -0.5 ? input capacitance c din 3 pf serial-port inputs (sclk, sdin, cs, where spen = 0v)?erial-port control mode allowable logic swing 0 - v avdd v input high threshold 1.5 v input low threshold 0.3 v v sclk /v sdin /v cs = v avdd = 1.8v or 3.3v +0.5 input leakage v sclk /v sdin /v cs = 0v -0.5 ? input capacitance c din 3 pf serial-port inputs (sclk, sdin, cs, where spen = v avdd )?arallel control mode (figure 5) v sclk /v sdin /v cs = v avdd = 1.8v 7 12 17 input pullup current v sclk /v sdin /v cs = v avdd = 3.3v 16 21 26 ? v sclk /v sdin /v cs = 0v, v avdd = 1.8v -65 -50 -35 input pulldown current v sclk /v sdin /v cs = 0v, v avdd = 3.3v -105 -90 -75 ? v avdd = 1.8v 1.35 1.45 1.55 open-circuit voltage v oc v avdd = 3.3v 2.58 2.68 2.78 v digital outputs (75 ? , d0?9 (a and b channel), dclka, dclkb, dora, dorb) output-voltage low v ol i sink = 200? 0.2 v output-voltage high v oh i source = 200? v ovdd - 0.2 v v ovdd applied +0.5 three-state leakage current i leak gnd applied -0.5 ?
max19515 ??1065msps adc 6 _______________________________________________________________________________________ electrical characteristics (continued) (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 65mhz, a in = -0.5dbfs, data output termination = 50?, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units power-management characteristics wake-up time from shutdown t wake internal reference, c refio = 0.1? (10 ) 5 ms wake-up time from standby t wake internal reference 15 ? serial-port interface timing (note 2) (figure 7) sclk period t sclk 50 ns sclk to cs setup time t css 10 ns sclk to cs hold time t csh 10 ns sdin to sclk setup time t sds serial-data write 10 ns sdin to sclk hold time t sdh serial-data write 0 ns sclk to sdin output data delay t sdd serial-data read 10 ns timing characteristics?ual bus parallel mode (figure 9) (default timing, see table 5) clock pulse-width high t ch 7.69 ns clock pulse-width low t cl 7.69 ns clock duty cycle t ch /t clk 30 to 70 % c l = 10pf, v ovdd = 1.8v (note 2) 3.4 5.3 7.1 data delay after rising edge of clk+ t dd c l = 10pf, v ovdd = 3.3v 4.1 ns data to dclk setup time t setup c l = 10pf, v ovdd = 1.8v (note 2) 12.8 13.4 ns data to dclk hold time t hold c l = 10pf, v ovdd = 1.8v (note 2) 1.4 2.0 ns timing characteristics?ultiplexed bus parallel mode (figure 10) (default timing, see table 5) clock pulse-width high t ch 7.69 ns clock pulse-width low t cl 7.69 ns clock duty cycle t ch /t clk 30 to 70 % c l = 10pf, v ovdd = 1.8v (note 2) 3.3 5.2 7.0 data delay after rising edge of clk+ t dd c l = 10pf, v ovdd = 3.3v 4.0 ns data to dclk setup time t setup c l = 10pf, v ovdd = 1.8v (note 2) 5.0 5.9 ns data to dclk hold time t hold c l = 10pf, v ovdd = 1.8v (note 2) 1.2 1.8 ns dclk duty cycle t dch /t clk c l = 10pf, v ovdd = 1.8v (note 2) 44 50 56 % mux data duty cycle t cha /t clk c l = 10pf, v ovdd = 1.8v (note 2) 44 50 56 % timing characteristics?ynchronization (figure 12) setup time for valid clock edge t suv edge mode (note 2) 0.7 ns hold-off time for invalid clock edge t sdh edge mode (note 2) 0.5 ns minimum synchronization pulse width relative to input clock period 2 cycles
max19515 ??1065msps adc _______________________________________________________________________________________ 7 electrical characteristics (continued) (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 65mhz, a in = -0.5dbfs, data output termination = 50?, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units power requirements low-level v avdd 1.7 1.9 analog supply voltage v avdd high-level v avdd (regulator mode, invoked automatically) 2.3 3.5 v digital output supply voltage v ovdd 1.7 3.5 v dual channel 47 55 single channel active 28 standby mode 8.5 12 power-down mode 0.65 0.9 analog supply current i avdd power-down mode, v avdd = 3.3v 1.6 ma dual channel 85 99 dual channel, v avdd = 3.3v 155 single channel active 50 standby mode 15 22 power-down mode 1.2 1.6 analog power dissipation p da power-down mode, v avdd = 3.3v 2.9 mw dual-channel mode, c l = 10pf 13 digital output supply current i ovdd power-down mode < 0.1 ma note 1: specifications +25? guaranteed by production test, specifications < +25? guaranteed by design and characterization. note 2: guaranteed by design and characterization.
175mhz two-tone imd frequency (mhz) amplitude (dbfs) max19515 toc06 -120 -100 -80 -60 -40 -20 0 f in1 = 172.49286mhz f in2 = 177.50202mhz 0 5 10 15 25 30 20 70mhz two-tone imd plot frequency (mhz) amplitude (dbfs) max19515 toc05 -120 -100 -80 -60 -40 -20 0 f in1 = 71.496925mhz f in2 = 68.504600mhz 0 5 10 15 25 30 20 175mhz input fft plot frequency (mhz) amplitude (dbfs) max19515 toc04 -120 -100 -80 -60 -40 -20 0 0 5 10 15 25 30 20 f in = 175.096626mhz a in = -0.512dbfs snr = 59.073db sinad = 59.022db thd = -78.338dbc sfdr1 = 81.806dbc sfdr2 = 84.255dbc 70mhz input fft plot frequency (mhz) amplitude (dbfs) max19515 toc03 -120 -100 -80 -60 -40 -20 0 0 5 10 15 25 30 20 f in = 70.1014328mhz a in = -0.532dbfs snr = 59.432db sinad = 58.388db thd = -79.349dbc sfdr1 = 84.227dbc sfdr2 = 81.877dbc 3mhz single-ended input fft plot frequency (mhz) amplitude (dbfs) max19515 toc02 -120 -100 -80 -60 -40 -20 0 0 5 10 15 25 30 20 f in = 2.99877166748047mhz a in = -0.546dbfs snr = 59.675db sinad = 59.632db thd = -79.673dbc sfdr1 = 88.737dbc sfdr2 = 82.290dbc max19515 ??1065msps adc 8 _______________________________________________________________________________________ _______________________________________________________________ ________ ? (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 65mhz, a in = -0.5dbfs, data output termination = 50?, t a = +25?, unless otherwise noted.) 3mhz input fft plot frequency (mhz) amplitude (dbfs) max19515 toc01 0 5 10 15 25 30 20 -120 -100 -80 -60 -40 -20 0 f in = 2.99877166mhz a in = -0.532dbfs snr = 59.682db sinad = 59.641db thd = -79.826dbc sfdr1 = 83.946dbc sfdr2 = 82.852dbc integral nonlinearity vs. digital output code digital output code inl (lsb) max19515 toc07 0 256 512 768 1024 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 differential nonlinearity vs. digital output code digital output code dnl (lsb) max19515 toc08 0 256 512 768 1024 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 performance vs. input frequency input frequency (mhz) performance (dbfs) max19515 toc09 0 50 100 150 200 250 300 350 400 50 55 60 65 70 75 80 85 90 95 -thd sinad sfdr1 snr sfdr2
analog supply current vs. supply voltage supply voltage (v) analog supply current (ma) max19515 toc18 1.65 1.70 1.75 1.80 1.85 1.90 1.95 40 41 42 43 44 45 46 47 48 49 50 performance vs. analog input amplitude analog input amplitude (dbfs) performance (dbfs) max19515 toc11 -80 -70 -60 -50 -40 -30 -20 -10 0 50 60 70 80 90 100 110 sfdr2 sfdr1 -thd sinad snr single-ended performance vs. input frequency input frequency (mhz) single-ended performance (dbfs) max19515 toc10 0 10 20 30 40 50 60 70 50 55 60 65 70 75 80 85 90 95 sfdr2 sfdr1 -thd sinad snr _______________________________________________________________ ____ ?() (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 65mhz, a in = -0.5dbfs, data output termination = 50?, t a = +25?, unless otherwise noted.) max19515 ??1065msps adc _______________________________________________________________________________________ 9 performance vs. sampling frequency sampling frequency (msps) performance (dbfs) max19515 toc12 20 25 30 35 40 45 50 55 60 65 70 50 55 60 65 70 75 80 85 90 95 sfdr1 sfdr2 -thd sinad snr performance vs. common-mode voltage common-mode voltage (v) performance (dbfs) max19515 toc13 0.35 0.55 0.75 0.95 1.15 1.35 50 55 60 65 70 75 80 85 90 95 sfdr2 sfdr1 -thd sinad snr performance vs. analog supply voltage analog supply voltage (v) performance (dbfs) max19515 toc14 1.65 1.70 1.75 1.80 1.85 1.90 1.95 50 55 60 65 70 75 80 85 90 sfdr2 sfdr1 -thd sinad snr performance vs. analog supply voltage analog supply voltage (v) performance (dbfs) max19515 toc15 2.3 2.5 2.7 2.9 3.1 3.3 3.5 50 55 60 65 70 75 80 85 90 sfdr2 sfdr1 -thd sinad snr analog supply current vs. sampling frequency sampling frequency (mhz) analog supply current (ma) max19515 toc16 20 25 30 35 40 45 50 55 60 65 70 30 32 34 36 38 40 42 44 46 48 50 analog supply current vs. temperature temperature (c) analog supply current (ma) max19515 toc17 -40 -20 0 20 40 60 80 40 41 42 43 44 45 46 47 48 49 50
10 ______________________________________________________________________________________ _______________________________________________________________ ____ ?() (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 65mhz, a in = -0.5dbfs, data output termination = 50?, t a = +25?, unless otherwise noted.) analog supply current vs. supply voltage supply voltage (v) analog supply current (ma) max19515 toc19 2.3 2.5 2.7 2.9 3.1 3.3 3.5 40 41 42 43 44 45 46 47 48 49 50 max19515 ??1065msps adc digital supply current vs. sampling frequency sampling frequency (msps) digital supply current (ma) max19515 toc20 20 25 30 35 40 45 50 55 60 65 70 0 2 4 6 8 10 12 v ovdd = 1.8v digital supply current vs. sampling frequency sampling frequency (msps) digital supply current (ma) max19515 toc21 20 25 30 35 40 45 50 55 60 65 70 0 5 10 15 20 25 v ovdd = 3.6v digital supply current vs. temperature temperature (c) supply current (ma) max19515 toc22 -40 -20 0 20 40 60 80 5 7 9 11 13 15 17 19 21 23 25 v ovdd = 3.6v v ovdd = 1.8v digital supply current vs. supply voltage supply voltage (v) digital supply current (ma) max19515 toc23 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 0 5 10 15 20 25 dual bus digital supply current vs. supply voltage supply voltage (v) digital supply current (ma) max19515 toc24 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 0 5 10 15 20 25 30 multiplexed bus performance vs. clock duty cycle clock duty cycle (%) performance (dbfs) max19515 toc25 30 35 40 45 50 55 60 65 55 60 65 70 75 80 85 90 sfdr1 -thd sfdr2 snr sinad performance vs. temperature temperature (c) performance (dbfs) max19515 toc26 -40 -20 0 20 40 60 80 50 55 60 65 70 75 80 85 90 95 sfdr2 sfdr1 -thd sinad snr gain error vs. temperature temperature (c) gain error (%) max19515 toc27 -40 -20 0 20 40 60 80 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05
_______________________________________________________________ ____ ?() (v avdd = v ovdd = 1.8v, internal reference, differential clock, v clk = 1.5v p-p , f clk = 65mhz, a in = -0.5dbfs, data output termination = 50?, t a = +25?, unless otherwise noted.) common-mode reference voltage vs. temperature temperature (c) common-mode reference voltage (v) max19515 toc30 -40 -20 0 20 40 60 80 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 v cm = 1.2v v cm = 1.05v v cm = 0.9v v cm = 0.75v v cm = 0.6v v cm = 0.45v v cm = 1.35v offset error vs. temperature temperature (c) offset error (mv) max19515 toc28 -40 -20 0 20 40 60 80 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 max19515 ??1065msps adc ______________________________________________________________________________________ 11 reference voltage vs. temperature temperature (c) reference voltage (v) max19515 toc29 -40 -20 0 20 40 60 80 1.2432 1.2453 1.2474 1.2495 1.2516 gain error vs. supply voltage supply voltage (v) gain error (%) max19515 toc31 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 regulator mode input current vs. common-mode voltage common-mode voltage (v) input current (a) max19515 toc32 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 20 25 30 35 40 45 50 55 60
max19515 ??1065msps adc 12 ______________________________________________________________________________________ 1, 12, 13, 48 avdd 2 cma 3 ina+ 4 ina- 5 spen 6 refio 7 shdn 8 i.c. 9 inb+ 10 inb- 11 cmb 14 sync 15 clk+ 16 clk- 17, 18 gnd 19 dorb 20 dclkb 21 d0b 22 d1b 23 d2b 24 d3b 25, 36 ovdd 26 d4b 27 d5b 28 d6b 29 d7b 30 d8b 31 d9b 32 d0a 33 d1a 34 d2a 35 d3a 37 d4a 38 d5a 39 d6a _______________________________________________________________ ____________ ? ???0.1 f??avdd(148)(1213)gnd ?a???? ?a?? ?a??? ??spi??????????? ?/??????0.1 f??gnd?? ? ?/(refio) ? ????? spen ???(???)shdn?? ??? ?b?? ?b??? ?b???? ??????? ?? ???clk-??clk+?????clk+/clk-?? ?? ?ep (?)? ?b?? ?b?? ?b?0(lsb) ?b?1 ?b?2 ?b?3 ????0.1 f??ovddgnd ?b?4 ?b?5 ?b?6 ?b?7 ?b?8 ?b?9(msb) ?a?0(lsb) ?a?1 ?a?2 ?a?3 ?a?4 ?a?5 ?a?6
max19515 ??1065msps adc ______________________________________________________________________________________ 13 _______________________________ ?? max1951510?????(?1)? ??????? ??????? ?9???????? ????? ???? ??adc??????2 ??max19515??? ???? ????(ina+/ina-inb+/inb-)? (?3)??? ???????? ?????adc? ??9??? ????????? ??? ??????2k ? ??? ???????? ????? ?????? ????2k ? ?? (?3)????? ????????? ?0.45v1.35v?0.15v? ???0.90v???? ??? 40 d7a 41 d8a 42 d9a 43 dora 44 dclka 45 sdin/format 46 sclk/div 47 cs /outsel ? ep max19515 + ? digital error correction flash adc x2 dac stage 2 in_+ in_- stage 1 stage 9 stage 10 end of pipeline d0_ through d9_ ?1. ??? ?? ____________________________________________________________________________ ?() ?a?7 ?a?8 ?a?9(msb) ?a?? ?a?? spi/? spen ?????? spen ?????? ?/??? spen ??????? spen ???????? ?/?? spen ???????? spen ??????? ???gnd??????
max19515 ??1065msps adc 14 ______________________________________________________________________________________ t/h ina+ cma refio cmb ina- output drivers data and output format pipeline adc pipeline adc clock clock digital error correction internal reference generator reference and bias system digital error correction duty- cycle equalizer clock divider d0a?9a dclkb shdn gnd dorb d0b?9b ovdd (1.8v to 3.3v) avdd (1.8v or 2.5v to 3.3v) dclka dora t/h inb+ inb- clk+ clk- sync cs sclk sdin serial port and control registers internal control 1.8v internal regulator and power control spen max19515 max19515 c par 0.7pf ina+ *v com *v com programmable from 0.45v to 1.35v. see common-mode register (08h) avdd cma 2k? 2k? c sample 1.2pf c sample 1.2pf c par 0.7pf ina- avdd sampling clock r switch 120? r switch 120? ?2. ?? ?3. ?(t/h)
max19515 ??1065msps adc ______________________________________________________________________________________ 15 ?/(refio) refio ????adc??4? ?????????????? ?????10k ? ?refio ?0.1 f?refiognd ??? ????? ???adc ????refio??? ?adc??+5/-15%refio adc?? v fs = 1.5 x [v refio /1.25] ??? ??max19515 ???spi? ??????@ ???? spen ??? spen ? ???spi?? spen ???????? ?????? ????? spen avdd???? 1??????5 bandgap reference buffer 1.250v refio internal gain?ypass refio external gain control?rive refio scale and level shift internal reference (controls adc gain) 10k? 0.1f external bypass ?4. ?????? 36k? 156k? cs sclk sdin avdd 29/32 avdd decoder to control logic 23/32 avdd 3/32 avdd ?5. ????? spen sdin/format sclk/div cs/outsel description 0 sdin sclk cs spi interface active. features are programmed through the serial port (see the serial programming interface section). 1 0 x x two? complement 1 avdd x x offset binary 1 unconnected x x gray code 1 x 0 x clock divide-by-1 1 x avdd x clock divide-by-2 1 x unconnected x clock divide-by-4 1 x x 0 cmos (dual bus) 1 x x avdd mux cmos (channel a data bus) 1 x x unconnected mux cmos (channel b data bus) 1. ? x = ??
max19515 ??1065msps adc 16 ______________________________________________________________________________________ ?? ? cs sdinsclkmax19515??? ? cs ????sclk? ? sdin cs ????max19515 sdinsclk? ?/cs? ??? sdin?????? ????????? ??????/??max19515 ; ?????max19515max19515 ?6?????sdin?? (01) 7?????? 8sdin ????????? msb???max19515scl k8 ????? (d7)sdinsdin ???sclk?8 ????sdinsclk ?sdinsclk? ?7???? r/w a6 a4a5 a2a3 a0a1 d7 d6 d4d5 d2d3 d0d1 r/w 0 = write 1 = read cs sclk sdin address data write or read cs t css t csh t sdd t sds t sdh t sclk sclk sdin write read ?6. ? ?7. ??
max19515 ??1065msps adc ______________________________________________________________________________________ 17 bit no. value description 7 0 reserved 6 0 reserved 5 0 or 1 1 = rom read in progress 4 0 or 1 1 = rom read completed and register data is valid (checksum is ok) 3 0 reserved 2 1 reserved 1 0 or 1 reserved 0 0 or 1 1 = duty-cycle equalizer dll is locked 2. ?0ah??? address por default function 00h 00000011 power management 01h 00000000 output format 02h 00000000 digital output power management 03h 10000000 data/dclk timing 04h 00000000 c h a d ata outp ut ter m i nati on contr ol 05h 00000000 c h b d ata outp ut ter m i nati on contr ol 06h 00000000 c l ock d i vi d e/d ata for m at/test p atter n 07h reserved reserved?o not use 08h 00000000 common mode 0ah software reset 3. ??? ??0ah??????5ah ?0ah???? ??????0ah?? ???2??? shdn(7)????? ????????? ?shdn = 1??max19515shdn = 0?? ??? ??? ?(00h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hps_shdn1 stby_shdn1 c h b_on _s h d n 1 c h a_o n _s h d n 1 hps_shdn0 stby_shdn0 chb_on_shdn0 c h a_o n _s h d n 0
max19515 ??1065msps adc 18 ______________________________________________________________________________________ hps_shdn0 stby_shdn0 cha_on_shdn0 chb_on_shdn0 shdn input = 0* hps_shdn1 stby_shdn1 cha_on_shdn1 chb_on_shdn1 shdn input = 1** x 0 0 0 complete power-down 0 0 0 1 channel b active, channel a full power-down 0 0 1 0 channel a active, channel b full power-down 0 x 1 1 channels a and b active 0 1 0 0 channels a and b in standby mode 0 1 0 1 channel b active, channel a standby 0 1 1 0 channel a active, channel b standby 1 1 0 0 channels a and b in standby mode 1 x x 1 channels a and b active, output is averaged 1 x 1 x channels a and b active, output is averaged ?(01h) ??? hps_shdn1hps_shdn0 a+b ????????? mux_ch ?(a+b)/2?? bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 bit_order_b bit_order_a mux_ch mux 0 * shdn = 0?hps_shdn0stby_shdn0cha_on_shdn0chb_on_shdn0 ** shdn = 1?hps_shdn1stby_shdn1cha_on_shdn1chb_on_shdn1 x = ?? ? hps_shdn_ = 1 (a+b???)?cha_on_shdn_chb_on_shdn_ 0?????? 765 0 4 bit_order_bchb? 0 = ??(?) 1 = ?? 3 bit_order_acha? 0 = ??(?) 1 = ?? 2 mux_ch? 0 = cha?(cha?chb) (?) 1 = chb?(chb?cha) 1 mux?? 0 = ???(?) 1 = ?? mux_ch? 0 0
max19515 ??1065msps adc ______________________________________________________________________________________ 19 ?(02h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x x x pd_dout_1 pd_dout_0 dis_dor dis_dclk 7 4 ? 32 pd_dout_1pd_dout_0??? 00 = ??(?) 01 = ??? 10 = ?? 11 = ??? 1 dis_dordor 0 = dor(?) 1 = dor(?) 0 dis_dclkdclk 0 = dclk(?) 1 = dclk(?)
max19515 ??1065msps adc 20 ______________________________________________________________________________________ /dclk?(03h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 da_bypass dly_half_t dclktime_2 dclktime_1 dclktime_0 dtime_2 dtime_1 dtime_0 7 da_bypass?? 0 = ??? 1 = ??????? dtime = 000b???????6ns (?) 6 dly_half_t?dclk?t/2 0 = ????(?) 1 = ?dclk?t/2 mux??? 543 dclktime_2dclktime_1dclktime_0dclk?(?) 000 = ???(?) 001 = +t/16 010 = +2t/16 011 = +3t/16 100 = ?? 101 = -1t/16 110 = -2t/16 111 = -3t/16 210 dtime_2dtime_1dtime_0?(?) 000 = ???(?) 001 = +t/16 010 = +2t/16 011 = +3t/16 100 = ?? 101 = -1t/16 110 = -2t/16 111 = -3t/16
max19515 ??1065msps adc ______________________________________________________________________________________ 21 cha??(04h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x ct_dclk_2_a ct_dclk_1_a ct_dclk_0_a ct_data_2_a ct_data_1_a ct_data_0_a 76 ? 543 ct_dclk_2_act_dclk_1_act_dclk_0_acha dclk?? 000 = 50 ? (?) 001 = 75 ? 010 = 100 ? 011 = 150 ? 1xx = 300 ? 210 ct_data_2_act_data_1_act_data_0_acha?? 000 = 50 ? (?) 001 = 75 ? 010 = 100 ? 011 = 150 ? 1xx = 300 ? chb??(05h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 x x ct_dclk_2_b ct_dclk_1_b ct_dclk_0_b ct_data_2_b ct_data_1_b ct_data_0_b 76 ? 543 ct_dclk_2_bct_dclk_1_bct_dclk_0_bchb dclk?? 000 = 50 ? (?) 001 = 75 ? 010 = 100 ? 011 = 150 ? 1xx = 300 ? 210 ct_data_2_bct_data_1_bct_data_0_bchb?? 000 = 50 ? (?) 001 = 75 ? 010 = 100 ? 011 = 150 ? 1xx = 300 ?
max19515 ??1065msps adc 22 ______________________________________________________________________________________ ???/??/?(06h) (07h) ?? bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 test_pattern test_data format_1 format_0 term_100 sync_mode div1 div0 7 test_pattern?? 0 = 01023 (??)?(?) (?) 1 = ??d[9:0] = 0101010101dor = 1d[9:0] = 1010101010dor = 0 6 test_data??? 0 = ?(?) 1 = ? 54 format_1format_0? 00 = ?(?) 01 = ?? 10 = 11 = ? 3 term_100?100 ? ?? 0 = ??(?) 1 = ?100 ? ? 2 sync_mode????? 0 = ??(?11) (?) 1 = ??(?12) 10 div1div0???? 00 = ??(?) 01 = 2? 10 = 4? 11 = ??
max19515 ??1065msps adc ______________________________________________________________________________________ 23 ?(08h) (0ah) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmi_self_b cmi_adj_2_b cmi_adj_1_b cmi_adj_0_b cmi_self_a cmi_adj_2_a cmi_adj_1_a cmi_adj_0_a 7 cmi_self_bchb??? 0 = ????(?) 1 = ?2k ? ????? 654 cmi_adj_2_bcmi_adj_1_bcmi_adj_0_bchb??? 000 = 0.900v (?) 001 = 1.050v 010 = 1.200v 011 = 1.350v 100 = 0.900v 101 = 0.750v 110 = 0.600v 111 = 0.450v 3 cmi_self_acha??? 0 = ????(?) 1 = ?2k ? ????? 210 cmi_adj_2_acmi_adj_1_acmi_adj_0_acha?? 000 = 0.900v (?) 001 = 1.050v 010 = 1.200v 011 = 1.350v 100 = 0.900v 101 = 0.750v 110 = 0.600v 111 = 0.450v 7 0 swreset5ah?
? ?????????? max19515??????????? ????clk+clk-? ????????? ???1v1.4v??? ?????????? ??clk-gnd??? clk+?clk-?(??? ??)?? ??? ??? max19515??????div0 div1?????????? ???/??/??(06h) ?(spen = 1)?div???? max19515 ??1065msps adc 24 ______________________________________________________________________________________ clk+ 100? termination (programmable) self-bias turned off for single-ended clock or power-down. clk- gnd avdd 10k? 20k? 5k? 5k? 50? 50? 2:1 mux select threshold ?8. ????? dclk data, dor sample clock n n+1 sample on rising edge n+2 n+4 n+5 n-9 n-8 n-10 n-7 n-6 n-5 n-4 t clk t setup t ch t dd t dc t hold t cl dual-bus output mode sample clock is the derived clock from (clk+ - clk-)/clock divider, in_ = in_+ - in_-. sampling instant sampling instant sampling instant sampling instant sampling instant sampling instant in_ t ad n+3 ?9. ????
max19515 ??1065msps adc ______________________________________________________________________________________ 25 ???? ?9?10????? ???max19515??? 9??????dclk ?????? ?????? [(clk+ - clk-)/divider] ? ?????????fpga ?max19515?????? ??????????/ ??/??(06h)sync_mode (2)? ???sync???? ???sync_mode = 0 (?) sync (???)??3?(clk) ????????(?11) ???sync_mode = 1 sync( ???)??3?(clk) ??????0?sync ??????clk?4(/2??) 5(/4??)(?12) dclk data, dor sample clock n-9 cha chb n-9 n-8 cha chb n-8 chb n-10 n-7 cha chb n-7 n-6 cha chb n-6 n-5 cha chb n-5 n-4 cha chb n-4 mux output mode in_ sampling instant sampling instant sampling instant sampling instant sampling instant sampling instant t ad n n+1 n+2 n+4 n+5 n+3 t ch t cl sample on rising edge t dc t dd t cha t dch t setup t hold t hold t dcl t setup t chb sample clock is the derived clock from (clk+ - clk-)/clock divider, in_ = in_+ - in_-. mux_ch (bit 2, output format 01h) determines the output bus and which channel data is presented. t clk ?10. ???
max19515 ??1065msps adc 26 ______________________________________________________________________________________ sync sync 2x input clk 4x input clk 1x divided clk (state) 1x divided clk (state) t suv = set-up time for valid clock edge. t ho = hold-off time for invalid clock edge. divide-by-2 slip syncronization 1234 1234 slip slip (1) (0) (1) (0) (1) (0) (1) (1) (0) (1) (0) (1) (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (0) (0) divide-by-4 slip synchronization 5 (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (3) (0) (1) (2) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) t ho t suv t ho t suv ?11. ???
max19515 ??1065msps adc ______________________________________________________________________________________ 27 sync sync 2x input clk 4x input clk 1x divided clk (state) 1x divided clk (state) t suv = set-up time for valid clock edge. t ho = hold-off time for invalid clock edge. divide-by-2 edge syncronization t ho t suv t ho t suv 1234 1234 (1) (0) (1) (0) (1) (0) (1) (0) (1) (1) (0) (1) (0) force to 0 force to 0 (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (0) divide-by-4 edge synchronization 5 (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (1) (2) (3) (0) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (3) (0) (1) (2) ?12. ???
max19515 ??1065msps adc 28 ______________________________________________________________________________________ max19515??cmos???? ????format??? ?(d0_ d9_)outsel ????spi? ?????(01h)spi? ?d0_ d9_???lsb d9_?msbd0_?ovdd ?1.8v3.3v?ovdd? 50 ? 300 ? ?ch_ ???(04h05h)?? ?? max19515?????? ???????? ??adc?? ????45?? ??????? ????13?14x? ?y???????dtime dly_half_t14???????? ??? max19515 65msps adc ???? 6?7???? ??????? ?15?16? da_bypass = 1?dclktime??? dtime??8? ? shdn(7)????? ??(00h)????? ???shdn = 1??max19515shdn = 0? ?????????shdn ?shdn?????? ?????(00h)? adc??????? ?????????? ?????? ??????????? ???????15 s?? ???????? ????????? ??????? ????????5ms?? refiorc?? 4. ? data timing control default description da_bypass 1 data aligner disabled dly_half_t 0 no delay dtime<2:0> 000 no delay dclktime<2:0> 000 no delay 5. ?? data timing control description da_bypass data aligner bypass. when this control is active (high), data and dclk delay is reduced by approximately 3.4ns (relative to da_bypass = 0). dly_half_t when this control is active, data output is delayed by half clock period (t/2). this control does not delay data output if mux mode is active. dtime<2:0> allows adjustment of data output delay in t/16 increments, where t is the sample clock period. dclktime<2:0> provides adjustment of dclk delay in t/16 increments, where t is the sample clock period. when dtime and dclktime are adjusted to the same setting, the rising edge of dclk occurs t/8 prior to data transitions.
max19515 ??1065msps adc ______________________________________________________________________________________ 29 ?15. ??(v ovdd = 1.8v) ?16. ??(v ovdd = 3.3v) 6. ??(v ovdd = 1.8v) ?13. ??(v ovdd = 1.8v) ?14. ??(v ovdd = 3.3v) recommended data timing vs. sample rate max19515 fig15 sampling rate (msps) data delay (t fractional period) 50 40 0.5 1.0 1.5 2.0 0 30 60 v ovdd = 1.8v da_bypass = 1 +11/16 +10/16 +9/16 +8/16 +7/16 +6/16 +3/16 +2/16 +1/16 0 -1/16 -2/16 -3/16 +5/16 recommended data timing vs. sample rate max19515 fig16 sampling rate (msps) data delay (t fractional period) 50 40 0.5 1.0 1.5 2.0 0 30 60 v ovdd = 3.3v da_bypass = 1 +11/16 +10/16 +9/16 +8/16 +7/16 +6/16 +3/16 +2/16 +1/16 0 -1/16 -2/16 -3/16 +5/16 factory-default nominal data timing vs. sample rate max19515 fig13 sampling rate (msps) data delay (t fractional period) 50 40 0.5 1.0 1.5 2.0 0 30 60 v ovdd = 1.8v da_bypass = 1 +11/16 +10/16 +9/16 +8/16 +7/16 +6/16 +3/16 +2/16 +1/16 0 -1/16 -2/16 -3/16 +5/16 factory-default nominal data timing vs. sample rate max19515 fig14 sampling rate (msps) data delay (t fractional period) 50 40 0.5 1.0 1.5 2.0 0 30 60 v ovdd = 3.3v da_bypass = 1 +11/16 +10/16 +9/16 +8/16 +7/16 +6/16 +3/16 +2/16 +1/16 0 -1/16 -2/16 -3/16 +5/16 sampling rate (msps) v ovdd = 1.8v from to da_bypass dly_half_t dtime<2:0> dclktime<2:0> 30 56 1 0 000 000 56 65 1 0 101 101
max19515 ??1065msps adc 30 ______________________________________________________________________________________ ?? max19515??(avdd)??? ??17?avdd???2v?? ??? avdd?2v?????? ???????? 1.8v??2.3v3.5v avdd?? ?1.8v?????? ?????? ? ?? ??????? ?????? avdd????? ??avdd???????avdd ????????? ??????? spen shdn?? ?adc???65msps??130 s 9??? 7. ??(v ovdd = 3.3v) dtime<2:0> allowed dclktime<2:0> settings 111 (-3t/16) 111 (-3t/16) 110 (-2t/16) 110 (-2t/16); 111 (-3t/16) 101 (-1t/16) 101 (-1t/16); 110 (-2t/16); 111 (-3t/16) 000 (nominal) 000 (nominal); 101 (-1t/16); 110 (-2t/16); 111 (-3t/16) 001 (+1t/16) 001 (+1t/16); 000 (nominal); 101 (-1t/16); 110 (-2t/16); 111 (-3t/16) 010 (+2t/16) 010 (+2t/16); 001 (+1t/16); 000 (nominal); 101 (-1t/16); 110 (-2t/16); 111 (-3t/16) 011 (+3t/16) 011 (+3t/16); 010 (+2t/16); 001 (+1t/16); 000 (nominal); 101 (-1t/16); 110 (-2t/16); 111 (-3t/16) 8. da_bypass = 1?dclktimedtime reset mode description power-on reset upon power-up (avdd supply voltage and clock signal applied), the por (power-on-reset) circuit initiates a register reset. software reset write data 5ah to address 0ah to initiate register reset. hardware reset a register reset is initiated by the falling edge on the shdn pin when spen is high. 9. sampling rate (msps) v ovdd = 3.3v from to da_bypass dly_half_t dtime<2:0> dclktime<2:0> 30 65 1 0 000 000
max19515 ??1065msps adc ______________________________________________________________________________________ 31 _______________________________ ?? ? ??? max19515???? sfdrthd???? ?????????? adc????? rf?(?18)???????? ?????cm_? ????1:1.4??? ???????? ???18???? (f clk /2)????? ?17. ?? in 2.3v to 3.5v enable out 1.8v regulator reference internal analog circuits avdd (pins 1, 12, 13, 48) gnd ?19. ??????? 1 5 3 6 2 4 n.c. v in 0.1f t1 mini-circuits adt1-1wt in_+ cm_ in_- n.c. 1 5 3 6 2 4 n.c. t2 mini-circuits adt1-1wt n.c. 75? 0.5% 75? 0.5% 110? 0.5% 110? 0.5% 0.1f max19515 ?18. ?????? max19515 1 5 3 6 2 4 n.c. n.c. v in 0.1f t1 mini-circuits adt1-1wt 36.5? 0.5% 36.5? 0.5% 0.1f in_+ cm_ in_-
max19515 ??1065msps adc 32 ______________________________________________________________________________________ ?19????????19 ???????? ????????75 ? 110 ? ?? ????50 ? ????? cm_????? ?? ?20???? max4108? ???????? 2k ? k??????? ?08h ? max19515 ???? (0.4v1.4v)?? ??????0.4v1.4v?? ? ?21????? ?? _____________________ J? max19515???J? ??adc???? ???0.1 f??? avddovddrefiocmacmbgnd ??????????? ????????? ??????? ?????????? ?90 ?? ___________________________________ ?(inl) inl????????? ?inl ??(dnl) dnl???1lsb??? 1 lsbdnl????? ??dnl?? ???dnl ? ?????? ???0.5lsb ??? ?? ?????? ?????? ???e???? ?20. ? max19515 0.1f 100? 100? 0.1f in_+ cm_ 0.1f in_- max4108 v in ?21. ? max19515 49.9? 49.9? 0.01f 0.1f 0.01f clk+ clk- clkin
max19515 ??1065msps adc ______________________________________________________________________________________ 33 ?(ssnf) ssnf??????? ?????? ????-35dbfs??? ??? ???? china .maxim-ic.com ????? (snr) ???snr? ?(rms?)rms(?)?? ?/?? ?adc??(n) snr [max] = 6.02 x n + 1.76 ???? ( ???)snrrms?rms? ?rms?(hd2 hd7) ????????? ? + ?(sinad) sinadrms?rms + rms??? rms?(hd2 hd7)?? ???????rms?? (hd2hd7) ??(sfdr1sfdr2) sfdr?(???)rms ???? ?????rms?????? sfdr1 ?23???sfdr2 ?23??? ?(thd) thd???rms??? ?? v 1 ??v 2 v 7 ?27(hd2 hd7) ? ?(im3) im3????? f in1 f in2 ?????????-7dbfs ??2 x f in1 - f in2 2 x f in2 - f in1 2 x f in1 + f in2 2 x f in2 + f in1 ?? ???????(t ad ) ??????? ? ?(t aj )????? ?? ??adc???? ??????? 10%? _______________________________ ?? process: cmos thd vvvvvv v log = +++++ ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 6 2 7 2 1 sinad noise distortion signal rms rms rms log = + ? ? ? ? ? ? ? ? 20 22 snr signal noise rms rms log = ? ? ? ? ? ? 20
top view max19515 13 14 15 16 17 18 19 20 21 22 23 24 avdd sync clk+ clk- gnd gnd dorb dclkb d0b d1b d2b d3b 48 47 46 45 44 43 42 41 40 39 38 37 1 2 345678910 11 12 avdd cs/outsel sclk/div sdin/format dclka dora d9a d8a d7a d6a d5a d4a avdd cmb inb- inb+ i.c. shdn refio spen ina- ina+ cma avdd 36 35 34 33 32 31 30 29 28 27 26 25 ovdd d4b d5b d6b d7b d8b d9b d0a d1a d2a d3a ovdd + *ep *exposed pad ____________________________________________________________________________ max19515 ??1065msps adc 34 ______________________________________________________________________________________ ____________________________________________________________________________ ?? ?????(?)? china.maxim-ic.com/packages ????+ # -? rohs?????????????rohs???? ? ? ?? 48 tqfn-ep t4877+4 21-0144 90-0130
0 7/08 ? 1 10/08 11 2 9/10 5, 6, 28, 29, 30 3 1/11 1 max19515 ??1065msps adc maximmaxim????????maxim??????????? maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ______________________ 35 2011 maxim integrated products maxim maxim integrated products, inc. ??? maxim 8328 100083 ?800 810 0310 010-6211 5199 010-6211 5299 ____________________________________________________________________________ ?? ? ? ? ?? ? ?32? cmos??? ?

▲Up To Search▲

Price & Availability of MAX1291ACEI-T

	To Download MAX1291ACEI-T Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .